In serial data transmit/receive systems, the clock information which provides the correct timing for data recovery is generally embedded in the data stream and there is no separate line or channel to carry a clock signal to the receiver. Clock frequency recovery and phase alignment with data is generally performed before the received data can be recovered and de-serialized. Traditionally, a Phase Locked Loop (PLL) is employed, in which the frequency of a Voltage Controlled Oscillator (VCO) is adjusted responsive to the incoming data frequency. The phase acquisition can be accomplished by the same phase locked Iccp, or by a separate phase locked Iccp depending on whether a single or a multi-loop system is used. The PLL detects the phase error of the recovered clock, or the phase difference between the output of the VCO and the incoming data and generates an error signal which is filtered and converted to a control voltage to drive the VCO to reduce the phase difference. When the phase difference of the two is eliminated or becomes a constant, the VCO output is truly a retimed clock since it has an established, known phase in relation to the data. In practice, the data is often contaminated with various types of noises such that timing or phase jitter is present. The edges i.e., the transitions, in the data stream do not always arrive perfectly in time, but rather at different "early" or "late" times, causing timing noise known as phase or timing jitter. Incorrect phase errors are detected and adjustments to the VCO control are still attempted even if the VCO frequency is the same or very close to the data frequency. The PLL is designed to reduce the effect of such jitter sources in the high frequency range by employing low pass filter such that the jitter of the recovered clock is limited and good stability of the Iccp achieved. However, heretofore this has been accomplished by introducing other problems. The control voltage to the VCO is susceptible to internally generated switching noise which is more serious when the operating frequency increases. The low pass filter function often employs components such as large values capacitors and resistors. These and other factors have made the monolithic integrated circuit implementation costly, especially when integrated with large scale, dense digital functions. Therefore, an all digital solution is highly desirable especially as feature dimensions of integrated circuits becomes smaller such that a complicated logic function may use smaller die area than even a single capacitor component.
In many prior art digital data recovery approaches, an adjustable bias voltage or current is employed to adjust the delay value of a delay unit in a ring oscillator to achieve frequency tuning or to adjust phase to match that of the incoming data. In these and other prior approaches, the techniques are generally specified for a certain data format, coding format, jitter tolerance or operation frequency. In a pending application "Digital Data Recovery Using Delay Time Rulers," assigned to the same assignee AMD Docket Number A860, Ser. No. 07/901,335 filed Jun. 19, 1992, data recovery is based on a discrete delay time rulers used for bit interval measurement. The time ruler in this earlier invention is generated from a local frequency reference source and possesses the correct frequency information for data recovery. However, the time ruler for subsequent bit time interval measurements is initiated upon the arrival of a data transition. Since the data are assumed to have a maximum edge-to-edge jitter of +/-25% of the bit period, the jitter tolerance for such a system is reduced to the same range. In another pending application " Digital Jitter Correction Method and Signal Preconditioner," also assigned to the same assignee, AMD Docket Number A862, Ser. No. 07/901,360 filed Jun. 19, 1992, jitter contributed from DCD (Duty Cycle Distortion) is detected and compensated using an all digital algorithmic method. Peak-to-peak jitter of an DCD compensated system with this approach may be reduced to less than +/-25% even when the original unadjusted peak-to-peak jitter is larger than +/-25%. However, the DCD compensation technique has a minimum improvement on jitter reduction if the DCD jitter is not dominant. A limitation of our previous time ruler data recovery scheme of our earlier filed application is that is restricted to short run length NRZI data. For long run length NRZI data stream, (consecutive data bits without transition), the accumulated timing error will eventually cause a failure since a finite error of the time ruler (or the delay value of the time ruler delay element) is always present; in other words, the jitter tolerance of my earlier system diminishes as the data run length increases. Since the design of some coding systems limit the run length of the encoded data, i.e. 4B/5B code used in Fiber Distributed Data Interface (FDDI), and the 8B/10B code used in FC (Fiber Channel), our earlier system was useful. However, other coding systems such as the systems using scrambled data, may not guarantee the run length limit. A need exists to have a general, all digital, time ruler based data recovery scheme which has much larger jitter tolerance than +/-25% of the bit period, and which does not deteriorate for longer run length, irrespective of the data or coding format employed.